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\title{A Framework for Memory Contention Analysis in Multi-Core Platforms\vspace{-5mm}}



\author{\IEEEauthorblockN{Dakshina Dasari$^{1}$, Vincent Nelis$^{1}$ and Benny Akesson$^{2}$}
\IEEEauthorblockA{$^{1}$CISTER/INESC-TEC Research Center, $^{2}$Czech Technical University in Prague }
\{dndi, nelis\}@isep.ipp.pt,kessoben@fel.cvut.cz
}

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\begin{abstract}
The last decade has witnessed a major shift towards the deployment of embedded applications on multi-core systems.
Real-time embedded applications having stringent timing requirements have not been able to avail the full benefits of these platforms, as 
the computational gains provided are often offset by performance degradation due to shared resources 
like the memory bus. Predictability is a central requirement for hard real-time systems, as their temporal behavior has to be analyzed at design time to make sure that all their timing constraints are met at run-time. However, shared memory buses are governed by different arbiters that are designed mainly with the aim of enhancing 
resource utilization and not towards predictability, hence making them difficult to analyze. 
A framework to upper bound the interference on the bus for different arbiters is thereby warranted, and this work is a step towards that aim. In this work, we clearly demarcate the arbiter-dependent and independent stages in the analysis of these bounds and propose a method to model the availability of the bus.  
Based on this bus model, we then design an algorithm to determine the maximum delay incurred by the tasks due to the contention for the shared bus. 
We demonstrate our framework by applying it to a memory bus shared by a work-conserving 
fixed-priority arbiter and a non-work-conserving time-division multiplexing arbiter.

\end{abstract}
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\section{Introduction}
\label{sec:intro}
\input{sections/intro.tex}
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\section{System Model}
\label{sec:model}
\input{sections/model.tex}
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\section{Overview of Approach}
\label{sec:probdef}
\input{sections/overview.tex}
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\section{Step 1: Modeling the Availability of the Bus}
\label{sec:bus_availability}
\input{sections/bus_availability.tex}
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\section{Step 2: Computing the W-C Delay for a Given Assignment}
\label{sec:wc_delay}
\input{sections/wc_delay.tex}
\section{Step 3: Finding the W-C Assignment}
\label{sec:wc_assignment}
\input{sections/wc_assignment.tex}
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\section{Step 4: Region-Wise Analysis}
\label{sec:complexity_reduction}
\input{sections/complexity_reduction.tex}
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\section{Experimental Results}
\label{sec:experiments}
\input{sections/experiments.tex}
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\section{Related Work}
\label{sec:related_work}
\input{sections/related_work.tex}
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\section{Conclusion}
\label{sec:conclusion}
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\appendix
\label{sec:appendix}
\input{sections/appendix.tex}
\end{document}

